Information processing device and method for sequence control and data processing

ABSTRACT

An information processing device includes a general-purpose personal computer 200, and a sequence engine 300 having a rudder interpreter 301 connected to the general-purpose personal computer 200 through a personal computer expansion bus 500. The rudder interpreter 301 executes a sequence instruction based on a predetermined sequence program in accordance with an instruction sent from the general-purpose personal computer 200. The general-purpose personal computer 200 performs information processing based on a predetermined information processing program, and executes peripheral processing in accordance with a peripheral processing request sent from the rudder interpreter 301.

TECHNICAL FIELD

The present invention relates to an information processing device and aninformation processing method for performing sequence processing such asprogrammable logic controller (which will be referred to as "PLC"hereinafter) as well as information processing, and in particularrelates to a device and a method for information processing, which allowinexpensive construction of a whole system using a general-purposecomputer, and also allow information processing with a minimum influenceexerted on a cycle of the sequence processing.

BACKGROUND ART

Such information processing devices have recently been proposed thatperform sequence processing of a PLC or the like utilizing ageneral-purpose personal computer, and also perform informationprocessing. These information processing devices utilizinggeneral-purpose personal computers can be classified into thefollowings:

(1) A type in which a PLC board is connected to a slot of ageneral-purpose computer (which will be referred to as a "board PLC").

(2) A type in which a general-purpose personal computer is added to aPLC (which will be referred to as a "PLC+personal computer"), and

(3) A type in which an intended function is provided by software on ageneral-purpose personal computer (which will be referred to as a"software PLC").

FIG. 16 is a block diagram showing a schematic structure of the boardPLC. Board PLC 15 has a structure in which a PLC board 20 is connectedto a slot of a general-purpose personal computer 10 (which will besimply referred to as a "personal computer" hereinafter) through apersonal computer expansion bus 30.

Personal computer 10 includes a microprocessor unit (MPU1) 11 and a workmemory 12.

PLC board 20 includes a ladder interpreter 21, a memory 22, amicroprocessor unit (MPU2) 23, a read-only memory (ROM) 24 and a buffer25.

Memory 22 includes a user memory UM for storing a ladder program whichis a user program, and an input/output memory IOM for storinginput/output information.

In the above structure, ladder interpreter 21 has a function as a buscontroller, so that microprocessor unit (MPU1) 11 of personal computer10 can access memory 22 of PLC board 20 through personal computerexpansion bus 30. ladder interpreter 21 can access work memory 12 ofpersonal computer 10 through personal computer expansion bus 30.

The processing of PLC can be basically classified into two kinds ofprocessing, i.e., "instruction execution" for interpreting and executinga ladder program and "peripheral processing" for performing inputrefreshing (IN-refreshing) and output refreshing (OUT-refreshing) of aninput/output port (I/O) and others.

In the board PLC shown in FIG. 16, the ladder interpreter 21 fetches anddecodes a ladder program stored in user memory UM of memory 22 for theabove "instruction execution".

Read-only memory (ROM) 24 in PLC board 20 has stored a peripheralprocessing program for the foregoing "peripheral processing".Microprocessor unit (MPU2) 23 executes the "peripheral processing" usingthe peripheral processing program stored in read-only memory (ROM) 24.

In the foregoing structure, personal computer 10 uses work memory 12 forexecuting predetermined information processing.

The "PLC+personal computer" described above differs from the above boardPLC in that the PLC is not formed of a PLC board structure, and isbasically the same as the PLC board.

FIG. 17 shows steps of processing by the above PLC and "PLC+personalcomputer". Although FIG. 17 shows the steps of processing by the boardPLC shown in FIG. 16, steps of processing by the "PLC+personal computer"are performed similarly to those shown in FIG. 17.

In FIG. 17, ladder interpreter 21 of PLC board 20 first fetches anddecodes a ladder program stored in user memory UM of memory 22 in PLCboard 20 for performing "instruction execution" (step S101). Results ofthis "instruction execution" are written into I/O memory IOM, andthereby the results of the "instruction execution" are reflected on I/Omemory IOM of memory 22 of PLC board 20. When one "instructionexecution" is completed, a request for "peripheral processing" is sentto microprocessor unit (MPU2) 23 of PLC board 20, and microprocessorunit (MPU2) 23 of PLC board 20 performs "peripheral processing" based ona peripheral processing program stored in read-only memory (ROM) 24(step S102).

Thereafter, personal computer 10 reads out contents of I/O memory IOMfor matching data held in personal computer 10 with data held in PLCboard 20 (i.e., data held in memory 22 of PLC board 20), and "dataexchange" is performed between personal computer 10 and PLC board 20(step S103).

Thereafter, the device operates similarly, and more specificallyperforms "instruction execution" by ladder interpreter 21 (step S104),"peripheral processing" by microprocessor unit (MPU2) 23 (step S105),"instruction execution" by ladder interpreter 21 (step S106),"peripheral processing" by microprocessor unit (MPU2) 23 (step S107),"data exchange" between personal computer 10 and PLC board 20 (stepS108), "instruction execution" by ladder interpreter 21 (step S109), and"peripheral processing" by microprocessor unit (MPU2) 23 (step S110).

Personal computer 10 performs predetermined "information processing"while "data exchange" is not being performed between personal computer10 and PLC board 20 of personal computer 10 (steps S112 and S113).

The board PLC and the "PLC+personal computer" are designed to operate asfollows. Microprocessor unit (MPU1) 11 of personal computer 10performing information processing is notified that "data exchange" isallowed every time PLC board 20 or the unillustrated PLC completes onecycle of sequence control formed of "instruction execution" and"peripheral processing". At this time, if microprocessor unit (MPU1) 11of personal computer 10 has already completed one cycle of "informationprocessing", "data exchange" is performed. If microprocessor unit (MPU1)11 of personal computer 10 has not yet completed one cycle of"information processing", "data exchange" is not performed, andmicroprocessor unit (MPU1) 11 of personal computer 10 continues"information processing". Thus, in the board PLC and the "PLC+personalcomputer", "information processing" by microprocessor unit (MPU1) 11 orpersonal computer 10 is performed in such a manner that "data exchange"between personal computer 10 and PLC board 20 is not performed duringone cycle of "information processing" from start to completion of"information processing".

FIG. 18 shows steps of processing by the foregoing software PLC. In thissoftware PLC, the "instruction execution", "peripheral processing" and"information processing" are performed only by personal computer 10shown in FIG. 16.

First, microprocessor unit (MPU1) 11 of personal computer 10 fetches anddecodes a ladder program stored in user memory UM to perform"instruction execution" (step S121). Then, microprocessor unit (MPU1) 11of personal computer 10 performs "peripheral processing" (step S122) and"data exchange" (step S124), and thereafter microprocessor unit (MPU1)11 of personal computer 10 performs "information processing" (stepS124).

Thereafter, the device operates similarly, and more specificallymicroprocessor unit (MPU1) 11 of personal computer 10 repeats"instruction execution" (step S125), "peripheral processing" (stepS125), "data exchange" (step S127) and "information processing" (stepS128).

In the above steps of processing by the software PLC, "informationprocessing" is performed each time "sequence control" is performedseveral times in view of a volume of "information processing" and aperiod of "sequence control" formed of "instruction execution" and"peripheral processing".

FIG. 19 is a flow chart specifically showing steps of processing of thesoftware PLC shown in FIG. 18. Referring to FIG. 19, upon start (stepS161), power-on and, in particular, initial setting are performed (stepS162), and then a ladder program stored in user memory UM is fetched anddecoded (step S163) to perform "instruction execution" (step S164).

The results of execution are written into I/O memory IOM, so that theresults of execution are reflected on I/O memory IOM (step S165).

Then, it is determined whether this "instruction execution" is completedor not (S166). If not (NO at step S166), the process returns to stepS163, and processing from step S163 to step S166 is repeated. If it isdetermined that "instruction execution" is completed (YES at step S166),peripheral processing such as I/O refreshing is then executed (stepS167).

It is determined whether the ladder program stored in user memory UM isentirely completed or not (step S168). If not (NO at step S168), theprocess returns to step S163. If it is determined that the ladderprogram is completed (YES at step S168), the process is completed (stepS169).

FIG. 20 is a flow chart showing steps of processing by the personalcomputer in the board PLC, the "PLC+personal computer" and the softwarePLC. When the personal computer starts up (step S131), it is firstdetermined whether a request for data exchange is present or not (stepS132). If present (YES at step S132), "data exchange" is performed (stepS133), and then "information processing" is executed (step S134). Then,it is determined whether "information processing" is completed or not(step S135). If not (NO at step S135), the process returns to step S134,and this "information processing" is continued. If it is determined that"information processing" is completed at step S135 (YES at step 135), itis then determined whether all the processing is completed or not (stepS136). If not (NO at step S136), the process returns to step S132, andprocessing from step S132 to step 136 is repeated. If it is determinedthat all the processing is completed at step S136 (YES at step S136),this process is completed (step S137).

FIG. 21 specifically shows steps of processing in the board PLC and the"PLC+personal computer". With reference to FIG. 21, description will begiven on the steps of processing by the board PLC shown in FIG. 16.However, the steps of processing by the "PLC+personal computer" aresubstantially the same as those shown in FIG. 21.

Referring to FIG. 21, upon start (step S141), microprocessor unit (MPU1)11 of personal computer 10 as well as microprocessor unit (MPU2) 23 andladder interpreter 21 of PLC board 20 are powered on, and initialsetting of them is performed (step S142). Then, start-up of PLC isinstructed (step S143), and thereby microprocessor unit (MPU2) 23 of PLCboard 20 instructs start-up of ladder interpreter 21 Step S151).

Upon start-up of ladder interpreter 21 of PLC board 20 (step S152),ladder interpreter 21 performs "instruction execution" by fetching anddecoding a ladder program stored in user memory UM of memory 22 in PLCboard 20 Step S153). Results of this execution are written into I/Omemory IOM of memory 22, so that the results of execution are reflectedon I/O memory IOM.

Upon completion of one "instruction execution", ladder interpreter 21sends a request for "peripheral processing" to microprocessor unit(MPU2) 23 of PLC board 20, and microprocessor unit (MPU2) 23 of PLCboard 20 performs "peripheral processing" based on a peripheralprocessing program stored in read-only memory (ROM) 24 Step S154).

Microprocessor unit (MPU1) 11 of personal computer 10 instructs start-upof PLC at step S143, and then determines whether data requiringinformation processing is present or not Step S144). If data requestinginformation processing is present (YES at step S144), "informationprocessing" is performed (step S145). When this "information processing"is completed, microprocessor unit (MPU2) 23 of PLC board 20 is notifiedthat data exchange is being waited for (step S146).

When it is determined that no data requiring information processing ispresent at step S144 (NO at step S144), the process advances to stepS146 without performing "information processing" at step S145, and thefact that data exchange is being waited for is notified tomicroprocessor unit (MPU2) 23 of PLC board 20.

When "peripheral processing" at step S154 is completed, microprocessorunit (MPU2) 23 of PLC board 20 determines whether microprocessor unit(MPU1) 11 of personal computer 10 has issued a notice of wait for dataexchange (step S155). If not (NO at step S155), the process returns tostep S153.

If it is determined that a notification of wait for data exchange ispresent at step S155 (YES at step S155), a notification that dataexchange is allowed is sent to microprocessor unit (MPU1) 11 of personalcomputer 10 (step S156).

Microprocessor unit (MPU1) 11 of personal computer 10 determines whetheror not microprocessor unit (MPU2) 23 of PLC board 20 has notified thatdata exchange is allowed, i.e., whether data exchange is allowed or not(step S147), after notifying microprocessor unit (MPU2) 23 of PLC board20 that data exchange is being waited. If data exchange is not allowed(NO at step S147), the process returns to step S146.

If it is determined that data exchange is allowed at step S147 (YES atstep S147), "data exchange" is performed between microprocessor unit(MPU1) 11 of personal computer 10 and microprocessor unit (MPU2) 23 ofPLC board 20 (steps S148 and S157).

Microprocessor unit (MPU1) 11 of personal computer 10 then determineswhether all "information processing" is completed or not (step S149). Ifall "information processing" is not completed (NO at step S149), theprocess returns to step S145, and processing from step S145 to step S149is repeated. When it is determined that all "information processing" iscompleted at step S149 (YES at step S149), microprocessor unit (MPU1) 11of personal computer 10 finishes the processing (step S150).

Microprocessor unit (MPU2) 23 of PLC board 20 determines whether all"sequence processing" is completed or not when "data exchange" iscompleted (step S158). If all "sequence processing" is not completed (NOat step S158), the process returns to step S153, and processing startingfrom step S153 are repeated. If it is determined that all "sequenceprocessing" is completed at step S158 (YES at step S158), processing bymicroprocessor unit (MPU2) 23 of PLC board 20 is finished (step S159).

The board PLC, "PLC+personal computer" and software PLC described aboverequire "data exchange" by reading out contents of I/O memory IOM by thepersonal computer. However, the determination whether "data exchange" bythe personal computer is to be performed or not is made only when"information processing" by the personal computer is finished. Thus,according to the board PLC, "PLC+personal computer" and software PLC,the personal computer continues "information processing" until the endof "information processing", and determines whether "data exchange" isto be performed or not when "information processing" is completed.

According to the software PLC, "information processing" operation isperformed only when a constant number of requests for data exchange arecounted. In this case, the above constant number is utilized to adjust aratio between times of "sequence control" and times of "informationprocessing".

The board PLC and the "PLC+personal computer" must employ dedicatedmicroprocessor units for performing the "instruction execution" and"peripheral processing" as well as memories for storing peripheralprocessing program, resulting in expensive structures.

According to the software PLC, a cycle of "sequence processing" and acycle of "information processing" are successively performed, so that along time is disadvantageously required before start of a subsequentcycle of "sequence control".

According to the software PLC, the user program is executed by fetchingand decoding the ladder program stored in user memory UM, and thereby"instruction execution" reflecting results of the execution on I/Omemory IOM is performed. After the ladder program stored in user memoryUM is entirely executed, "peripheral processing" is performed, andspecifically the state of each I/O port I/O is reflected on I/O memoryIOM by I/O refreshing. Since the foregoing operations are performed asone cycle of the process, an execution speed is disadvantageously slow.

Accordingly, an object of the present invention is to provide aninformation processing device and an information processing method,which allow an inexpensive structure of a whole system, and can performinformation processing with a minimized influence exerted on a cycle ofsequence processing.

Another object of the invention is to provide a device and a method forsequence control, which allow an inexpensive structure of a wholesystem, and can increase an execution speed.

DISCLOSURE OF THE INVENTION

An information processing device according to the invention includes adata processing device provided with a processor and an internal busconnected to the processor, and a sequence instruction execution unitconnected to the internal bus. In this information processing device,the data processing device or the sequence instruction execution unitincludes a user memory for storing a sequence program prepared by a userand an I/O memory for storing a status of input/output. AN I/O boardconnected to an external device controlled by an instruction of thesequence program is connected independently of the sequence instructionexecution unit to the internal bus.

Since the I/O board connected to the external device, which iscontrolled by the instruction of the sequence program prepared by theuser, is connected independently of the sequence instruction executionunit to the internal bus, the system construction can be simplified.Further, no mutual interference occurs between the operation of theexternal device and the operation of the sequence instruction executionunit controlled by the instruction of the sequence program, so thatinformation processing can be performed with a minimized influenceexerted on the cycle of the sequence processing.

According to another aspect, an information processing device includes adata processing device provided with a processor and an internal busconnected to the processor, and a sequence instruction execution unitconnected to the internal bus. The data processing device or thesequence instruction execution unit includes a user memory for storing asequence program prepared by a user and an I/O memory for storing astate of input/output. The information processing device furtherincludes an I/O board connected to the internal bus and having a memory,and is connected to an external device via the I/O board. The dataprocessing device includes an execution processing unit for executingpredetermined peripheral processing after interpretation and executionof an instruction in the user memory by the sequence instructionexecution unit.

The I/O board having the memory and connected to the external device isconnected independently of the sequence instruction execution unit tothe internal bus, and the predetermined peripheral processing isexecuted after interpretation and execution of the instruction in theuser memory by the sequence instruction execution unit. Therefore,transmission of data between the external device and the I/O memory orthe like is independently performed after execution of the instructionin the user memory, so that the whole system can have an inexpensivestructure, and an influence exerted on a cycle of sequence processingcan be minimized.

Preferably, the sequence program is formed of a ladder program, and thesequence instruction execution unit includes a ladder interpreterperforming instruction execution processing by interpreting andexecuting the ladder program.

More preferably, the sequence instruction execution unit includes aregister for managing the instruction execution processing by the ladderinterpreter.

Further preferably, the register includes a program counter registerhaving a value to be initially set upon start-up of the ladderinterpreter and incremented upon every execution of one instruction ofthe ladder program, a status register storing a status of execution ofthe ladder program by the ladder interpreter, and an address registerstoring a leading address of the ladder program executed by the ladderinterpreter.

Further preferably, the status register stores a first flag indicatingstart and stop of the ladder interpreter, and a second flag indicatingwhether the data processing device is to be requested to performinstruction execution processing with the ladder program or not.

According to still another aspect, the invention provides a sequencecontrol method including the step of connecting a sequence instructionexecution unit to a data processing device through a bus, and storing asequence program in a data processing device, wherein the sequenceinstruction execution unit includes the step of executing the sequenceprogram by accessing through the bus the sequence program stored in thedata processing device based on an instruction issued from the dataprocessing device.

In the sequence control method, since the sequence instruction executionunit executes the sequence program stored in the data processing devicebased on the instruction sent from the data processing device, it ispossible to provide the sequence control method, which can reduce a costof the whole system and can increase the execution speed.

According to further another aspect of the invention, a sequence enginenot having a function of executing peripheral processing includes aladder interpreter connected to an internal bus of a data processingdevice and activated by the data processing device to interpret andexecute a ladder instruction, and a register for managing and storing astatus of execution of the ladder program by the ladder interpreter.

Since the register manages and stores the status of execution of theladder program by the ladder interpreter which is started up by the dataprocessing device to interpret and execute the ladder instruction, thestatus of execution of the ladder program can be reliably managed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a schematic structure of a softwarePLC with a sequence engine employing a device and a method forinformation processing according to a first embodiment of the invention;

FIG. 2 shows steps of processing in the software PLC with the sequenceengine shown in FIG. 1;

FIG. 3 is a flow chart showing steps of information processing by amicroprocessor unit of a personal computer shown in FIG. 1;

FIG. 4 shows an example of a program counter register for informationprocessing employed in this embodiment;

FIG. 5 shows an example of a data address register employed in thisembodiment;

FIG. 6 shows an example of a data address register employed in thisembodiment;

FIG. 7 is a flow chart specifically showing steps of processing by asoftware PLC according to an embodiment of the invention shown in FIG.1;

FIG. 8 is a block diagram showing a schematic structure of the softwarePLC with sequence engine employing an information processing device of asecond embodiment of the invention;

FIG. 9 is a flow chart showing steps of processing in the software PLCwith the sequence engine of the second embodiment;

FIG. 10 shows an example of a program counter register forming aregister of the sequence engine in the second embodiment;

FIG. 11 shows an example of a status register forming the register ofthe sequence engine in the second embodiment;

FIG. 12 shows an example of an UM address register forming the registerof the sequence engine in the second embodiment;

FIG. 13 is a flow chart showing steps of processing of anotherembodiment of the invention, in which a microprocessor unit of apersonal computer supports instruction execution performed by a ladderinterpreter of the sequence engine in the second embodiment;

FIG. 14 shows another example of a status register in the embodiment ofthe invention shown in FIG. 13;

FIG. 15 shows transition of processing based on a start flag and an MPUexecution flag in the embodiment shown in FIG. 13;

FIG. 16 is a block diagram showing a schematic structure of a board PLCin the prior art;

FIG. 17 shows steps of processing by the board PLC and "PLC+personalcomputer";

FIG. 18 shows steps of processing by a software PLC;

FIG. 19 is a flow chart specifically showing steps of processing by thesoftware PLC;

FIG. 20 is a flow chart showing steps of information processing by apersonal computer in the board PLC, "PLC+personal computer" and softwarePLC; and

FIG. 21 is a flow chart specifically showing steps of processing in theboard PLC and "PLC+personal computer".

PREFERRED EMBODIMENTS FOR IMPLEMENTING THE INVENTION

The invention will be described below further in detail with referenceto the drawings.

(1) First Embodiment

Referring to FIG. 1, a software PLC 100 provided with a sequence engine,which is constructed by employing a device and a method for informationprocessing according to the invention, has such a structure that asequence engine 300 is connected to an internal bus 203 of a personalcomputer 200 through a personal computer expansion bus 500, and aninput/output board (i.e., I/O board) 400 is connected to internal bus203.

Personal computer 200 includes a microprocessor unit (MPU1) 201 and awork memory 202.

Sequence engine 300 includes a ladder interpreter 301 which interpretsand executes a ladder program stored in a user memory UM, a register 302which manages and stores a status of execution of the ladder program byladder interpreter 301, and a memory 303 having a user memory UM storingthe ladder program which is a user program and an I/O memory IOM storinginput/output information.

Since ladder interpreter 301 has a function as a bus controller,microprocessor unit (MPU1) 201 of personal computer 200 can accessregister 302 and memory 303 of sequence engine 300 through personalcomputer expansion bus 500. Also, ladder interpreter 301 can access workmemory 202 of personal computer 200 through personal computer expansionbus 500.

Input/output board (i.e., I/O board) 400 includes a buffer 401 whichtemporarily stores information sent into and from an input/output port(i.e., I/O port).

As already described, processing of the PLC can be basically classifiedinto "instruction execution" for interpreting and executing the ladderprogram and "peripheral processing" for performing input refreshing(which will be referred to as "IN-refreshing" hereinafter) and outputrefreshing (which will be referred to as "OUT-refreshing" hereinafter)of the I/O port.

Here, "peripheral processing" includes processing for storing data,which was sent from an external device and is stored in buffer 401 ofI/O board 400, in I/O memory IOM, and for sending data stored in the I/Omemory IOM to the external device through buffer 401.

In software PLC 100 with the sequence engine shown in FIG. 1 of thisembodiment, ladder interpreter 301 of sequence engine 300 performs theabove "instruction execution" by fetching and decoding the ladderprogram stored in user memory UM of memory 303, and results of the"instruction execution" are reflected on I/O memory IOM of memory 303.

Microprocessor unit (MPU1) 201 of personal computer 200 performs "dataexchange" by accessing I/O memory IOM of memory 303 through ladderinterpreter 301 of sequence engine 300, and performs "informationprocessing" based on a predetermined information processing program.

According to the above structure, it is not necessary to provide adedicated microprocessor unit and a dedicated memory at sequence engine300, so that the structure can be significantly inexpensive comparedwith board PLC 15 shown in FIG. 16. Further, "instruction execution" isperformed by dedicated hardware, i.e., ladder interpreter 301 ofsequence engine 300, so that processing can be faster than that by thesoftware PLC already described with reference to FIG. 18.

In this embodiment, a predetermined information processing programexecuted by microprocessor unit (MPU1) 201 of personal computer 200 isformed of a plurality of blocks, and, upon every completion ofprocessing of one block, microprocessor unit (MPU1) 201 of personalcomputer 200 determines whether a predetermined processing requestissued from sequence engine 300 is present or not.

Therefore, microprocessor unit (MPU1) 201 of personal computer 200 isdesigned such that, even during information processing, it can interrupt"information processing" and can execute "peripheral processing"whenever sequence engine 300 issues a request for peripheral processing.

In this embodiment, therefore, the internal status is saved in theregister upon every interruption of "information processing". When"information processing" is restarted after completion of "peripheralprocessing", the internal status saved in the register is read out forrestarting "information processing".

FIG. 2 shows steps of processing in software PLC 100 with the sequenceengine shown in FIG. 1. Referring to FIG. 2, ladder interpreter 301 ofsequence engine 300 first performs "instruction execution" by fetchingand decoding the ladder program stored in user memory UM of memory 303(step S211).

When ladder interpreter 301 of sequence engine 300 finishes this"instruction execution", ladder interpreter 301 of sequence engine 300sends a "peripheral processing request" to microprocessor unit (MPU1)201 of personal computer 200.

Microprocessor unit (MPU1) 201 of personal computer 200, which receivedthe "peripheral processing request" from ladder interpreter 301 ofsequence engine 300, executes "peripheral processing" (step S212). Whenthis "peripheral processing" is finished, microprocessor unit (MPU1) 201accesses I/O memory IOM of memory 303 of sequence engine 300 andperforms "data exchange", i.e., reading of data from I/O memory IOM(step S213). Thereafter, "information processing" is executed (stepS215). The information processing program of "information processing"executed by microprocessor unit (MPU1) 201 of personal computer 200 isformed of a plurality of (e.g., n) divided blocks. Microprocessor unit(MPU1) 201 of personal computer 200 first executes a first block of theinformation processing program, i.e., 1/n of the information processingprogram.

In ladder interpreter 301 of sequence engine 300, a next instruction inthe ladder program stored in user memory UM of memory 303 is fetched anddecoded to perform "instruction execution" when "data exchange" iscompleted (step S214).

When this "instruction execution" is completed, the "peripheralprocessing request" is sent to microprocessor unit (MPU1) 201 ofpersonal computer 200.

In microprocessor unit (MPU1) 201 of personal computer 200, whenexecution of the first block, i.e., 1/n of the information processingprogram is completed (step S215), predetermined "interruptionprocessing" is executed, and it is determined whether ladder interpreter301 of sequence engine 300 has issued a "peripheral processing request"or not.

In this case, since it is determined that ladder interpreter 301 ofsequence engine 300 has issued the "peripheral processing request","information processing" which is being performed is interrupted, andthe "peripheral processing" is executed (step S216).

Thereafter, processing is performed in a similar manner, and morespecifically, the device performs "instruction execution" by ladderinterpreter 301 of sequence engine 300 (step S217), "informationprocessing" by microprocessor unit (MPU1) 201 of personal computer 200(step S218), "peripheral processing" (step S219), "data exchange" (stepS220), "instruction execution" by ladder interpreter 301 of sequenceengine 300 (step S221), "information processing" by microprocessor unit(MPU1) 201 of personal computer 200 (step S222), and "peripheralprocessing" by microprocessor unit (MPU1) 201 of personal computer 200(step S223).

According to the above structure, microprocessor unit (MPU1) 201 ofpersonal computer 200 determines whether sequence engine 300 has issueda "peripheral processing request" or not upon every completion ofprocessing of one block. When the "peripheral processing request" hasbeen issued, "information processing" is interrupted and "peripheralprocessing" is executed. Therefore, "information processing" can beperformed with a minimum influence exerted on a cycle of "sequenceprocessing" performed by ladder interpreter 301 of sequence engine 300.

FIG. 3 is a flow chart showing steps of the information processing bymicroprocessor unit (MPU1) 201 of personal computer 200, andcorresponding to FIG. 20 already described.

In FIG. 3, when microprocessor unit (MPU1) 201 of personal computer 200is activated (step S231), it determines whether ladder interpreter 301of sequence engine 300 has issued the "peripheral processing request" ornot (step S232). When it is determined that ladder interpreter 301 ofsequence engine 300 has not issued the "peripheral processing request"(NO at step S232), the process returns to step S232. When it isdetermined that the "peripheral processing request" has been issued (YESat step S232), it is then determined whether "interruption processing"has been performed in microprocessor unit (MPU1) 201 of personalcomputer 200 or not (step S233). When "interruption processing" has notbeen performed (NO at step 233), "data exchange" is executed (stepS234), and then "information processing" is executed (step S235).

When it is determined that "interruption processing" has been performed(YES at step 233), the process advances to step S235 without performing"data exchange" at step S234, and "information processing" is executed.

Then, it is determined whether this "information processing" iscompleted or not (step S236). When it is determined that "informationprocessing" is not completed (NO at step S236), it is then determinedwhether ladder interpreter 301 of sequence engine 300 has issued a"peripheral processing request" or not (step S237). When the "peripheralprocessing request" has been issued (YES at step 237), "interruptionprocessing" of "information processing" is executed (step S238).

When it is determined, at step 236, that the "information processing" iscompleted (YES at step 236), the process returns to step S232. When itis determined at step S237 that the "peripheral processing request" hasnot been issued (NO at step S237), the process returns to step S235.

When "interruption processing" is completed at step S238, it is thendetermined whether all "information processing" is completed or not(step S239). When it is determined that all "information processing" isnot completed (NO at step S239), the process returns to step S232. Whenit is determined that all "information processing" is completed (YES atstep S239), this processing is finished (step S240).

In the software PLC with the sequence engine, since "instructionexecution" is performed by the dedicated hardware, i.e., ladderinterpreter 301 of sequence engine 300, fast processing is allowed.

Since the process is executed through the steps described above, itincludes processing for "start-up of sequence engine 300" and "stop ofsequence engine 300" based on the instructions from microprocessor unit(MPU1) 201 of personal computer 200.

The status of execution of the ladder program stored in user memory UMof memory 303 in sequence engine 300 is transferred betweenmicroprocessor unit (MPU1) 201 of personal computer 200 and ladderinterpreter 301 of sequence engine 300. For this purpose as well as"instruction execution" by ladder interpreter 301, ladder register 302of sequence engine 300 includes:

(1) a program counter register,

(2) a status register, and

(3) a UM address register.

The "start-up of sequence engine 300" is performed by such an operationthat microprocessor unit (MPU1) 201 of personal computer 200 sets theprogram counter register of register 302 in sequence engine 300 to aninitial value, and sets the "start flag" of the status register to thestart state.

When the "start flag" of status register is set to the start state,ladder interpreter 301 of sequence engine 300 refers to the initialvalue set at the program counter register, and starts fetching anddecoding of the ladder program stored in user memory UM of memory 303.

The "stop of sequence engine" is performed by setting the "start flag"of status register to the stop state.

When the "start flag" of status register is set to the stop state,ladder interpreter 301 of sequence engine 300 stops its processing, andnotifies microprocessor unit (MPU1) 201 of personal computer 200 of thisstop in an interrupting manner.

In the program counter register, the initial value is set upon start-upof ladder interpreter 301 of sequence engine 300, and is incrementedupon every execution of one instruction in the ladder program stored inuser memory UM.

The UM address register stores a leading address (UM leading address) ofthe ladder program stored in user memory UM of memory 303 for"instruction execution".

For "interruption processing" of "information processing" describedabove, personal computer 200 in this embodiment includes:

(4) a program counter register for information processing,

(5) a data address register, and

(6) a data size register.

These registers, i.e.,

(4) the program counter register for information processing,

(5) the data address register, and

(6) the data size register will be described below in detail.

FIG. 4 shows an example of the program counter register for informationprocessing. The program counter register for information processing isformed of two registers, i.e., a first register 311 of 16 bits and asecond register 312 of 16 bits. In the initial setting operation,microprocessor unit (MPU1) 201 of personal computer 200 keeps an area onwork memory 202. When interruption of "information processing" occurs,it holds a value of the program counter which manages the informationprocessing program for executing "information processing".

Here, 16 bits from a bit 0 to a bit 15 in first register 311 store anaddress H, which is a high address in the program counter at the time ofoccurrence of interruption of "information processing", and 16 bits froma bit 0 to a bit 15 in second register 312 store an address L, which isa low address in the program counter at the time of occurrence ofinterruption of "information processing". The initial value of thisprogram counter for information processing is set to "00000000h".

FIG. 5 shows an example of the data address register described before.Similarly to the program counter register for information processing,the data address register is formed of two registers, i.e., firstregister 313 of 16 bits and second register 314 of 16 bits. When settingthe initial value, microprocessor unit (MPU1) 201 of personal computer200 keeps an area for it on work memory area 202. When interruption of"information processing" occurs, it keeps a data block for holding theoutput of the information processing block already processed, and storesthe leading address of this data block.

Here, 16 bits from a bit 0 to a bit 15 in first register 313 store aleading address H of the data block, which is a high address of theleading address of the data block, and 16 bits from a bit 0 to a bit 15in second register 314 store a leading address L of the data block,which is a low address of the leading address of the data block. Theinitial value of this data address register is set to "00000000h".

FIG. 6 shows an example of the data size register. The data sizeregister is formed of a 16-bit register 315. In the initial setting,microprocessor unit (MPU1) 201 of personal computer 200 keeps an areafor it on work memory 202. When interruption of "information processing"occurs, it keeps a data block for holding the output of the informationprocessing block already processed, and stores the size (bytes) of thisdata block.

In this example, the size (bytes) of the data block is stored on eightbits from a bit 8 to a bit 15 in register 315, and eight bits from a bit0 to a bit 7 are set to reserve. The reserve of this data size is set to"0", and the initial value is set to "0000h". The size (bytes) of thedata block, which is stored in the data size register when interruptionof "information processing" does not occur, is "000h".

Description will now be given on specific steps of processing in thisembodiment.

FIG. 7 is a flow chart showing specific steps of the processing in thisembodiment. Referring to FIG. 7, power-on and initial setting are firstperformed (step S252) upon start-up (step S251).

For the initial setting, microprocessor unit (MPU1) 201 of personalcomputer 200 issues a reset signal to sequence engine 300 forinitializing the following units arranged in register 302 of sequenceengine 300.

(1) program counter register

(2) status register

(3) UM address register

Then, microprocessor unit (MPU1) 201 of personal computer 200 keeps, onwork memory 202, the areas for the following registers and therebyinitializes them.

(4) program counter register for information processing

(5) data address register

(6) data size register

Microprocessor unit (MPU1) 201 of personal computer 200 writes a UMleading address in the UM address register, and subsequently reads itfor determining whether the writing in the UM address register wasperformed successful or not. When the writing in the UM address registerwas succeeded, this initial setting is finished. If the writing in theUM address register was failed, writing in the UM address register isperformed again.

Then, microprocessor unit (MPU1) 201 of personal computer 200 effectsstart-up processing for ladder interpreter 301 of sequence engine 300(step S253).

The start-up processing for ladder interpreter 301 of sequence engine300 is performed by setting an initial value at the program counterregister of register 302 in sequence engine 300 and setting the "startflag" of the status register to the start status.

When ladder interpreter 301 of sequence engine 300 starts up (stepS264), ladder interpreter 301 performs "instruction execution" byfetching and decoding the ladder program stored in user memory UM ofmemory 303 (step S265). Results of this execution are written into I/Omemory IOM of memory 303, and thereby are reflected on I/O memory IOM.

When one "instruction execution" is finished, ladder interpreter 301sends a "peripheral processing request notification" requesting"peripheral processing" to microprocessor unit (MPU1) 201 of personalcomputer 200 (step S266), and thereafter stops (step S267).

When microprocessor unit (MPU1) 201 of personal computer 200 completesthe start-up processing for ladder interpreter 301 of sequence engine300, it determines whether the peripheral processing request issued fromladder interpreter 301 of sequence engine 300 is present or not (stepS254). When it is determined that the peripheral processing requestissued from ladder interpreter 301 of sequence engine 300 is present(YES at step S254), "peripheral processing" is executed (step S255).

It is then determined whether "interruption processing" was performed atmicroprocessor unit (MPU1) 201 of personal computer 200 or not (stepS256). When "interruption processing" was not performed (NO at stepS256), "data exchange" is executed (step S257), and thereafter"information processing" is executed (step S258).

When it is determined that "interruption processing" was performed atstep S256 (YES at step S256), the process advances to step S258 withoutperforming "data exchange" at step S257, and "information processing" isexecuted.

Then, it is determined whether this "information processing" iscompleted or not (step S259). When it is determined that this"information processing" is not completed (NO at step 259), it is thendetermined whether ladder interpreter 301 of sequence engine 300 hasissued a "peripheral processing request" or not (step S260). When the"peripheral processing request" has been issued (YES at step S260),"interruption processing" for interrupting "information processing" isexecuted (step S261).

When it is determined that "information processing" is completed at stepS259 (YES at step S259), the process returns to step S254. When it isdetermined at step S260 that "peripheral processing request" has notbeen issued (NO at step S260), the process returns to step S258.

When it is determined at step S254 that the "peripheral processingrequest" has not been issued (NO at step S254), it is determined whetherall "peripheral processing" is completed or not (step S262). When it isdetermined that all "information processing" is not completed (NO atstep S262), the process returns to step S254. When it is determined thatall "information processing" is completed (YES at step S262), it is themdetermined whether all "sequence processing" is completed or not (stepS263). When all "sequence processing" is not completed (NO at stepS263), the process returns to step S253. When all "sequence processing"is completed (YES at step S263), this process is finished (step S268).

In this embodiment, a predetermined information processing programexecuted by microprocessor unit (MPU1) 201 of personal computer 200 isformed of a plurality of blocks, and the microprocessor unit (MPU1) 201of personal computer 200 is adapted to interrupt "informationprocessing" at boundaries between these blocks. In order to restart theinterrupted "information processing", it is necessary to save theresults of processing of the information processing blocks which havealready been processed.

More specifically, in order to restart the interrupted "informationprocessing", the results of processing of Nth information processingblock already processed will form an input of (N+1)th informationprocessing block.

In this embodiment, it is determined, upon every completion of theinformation processing block, whether a "peripheral processing request"from sequence engine 300 is present or not, and "information processing"is interrupted in accordance with the following steps when the"peripheral processing request" is present.

(1) A program counter value is stored in the program counter registerfor information processing.

(2) An area corresponding to an amount of data output by "informationprocessing" is kept on work memory 202 of personal computer 200.

(3) A leading address of the data block is stored in the data addressregister.

(4) A size of the data block is stored in the data size register.

When conditions for enabling execution of "information processing" aresatisfied, "information processing" are restarted in accordance with thefollowing steps.

(1) A value stored in the program counter register for informationprocessing is read out, and is written into the program counter.

(2) The leading address of the data program stored in the data registeris read out.

(3) Data of only the data block size stored in the data size registerand starting from the leading address of the data block read at (2) isfetched and input.

In the above structure, presence or absence of "interruption processing"can be determined based on a value stored in "data size register". Thisis because of the following fact. As described before, when interruptionof "information processing" occurred, a size of the data block is storedin the "data size register". Alternatively, the value stored in the"data size register" is "000h" when interruption of "informationprocessing" did not occur.

(2) Second Embodiment

FIG. 8 is a block diagram showing a schematic structure of a softwarePLC 101 with a sequence engine, which employs a device and a method forsequence control according to a second embodiment.

In FIG. 8, software PLC 101 with the sequence engine has a structuresimilar to that of the first embodiment, and therefore has such astructure that sequence engine 300 is connected to internal bus 203 ofgeneral-purpose personal computer 200 via personal computer expansionbus 500, and I/O board 400 is also connected thereto. The same elementsand components as those in the first embodiment bear the same referencecharacters.

Personal computer 200 includes microprocessor unit (MPU1) 201 and workmemory 204, which is provided with a user memory UM storing a userprogram, i.e., ladder program and an I/O memory IOM storing input/outputinformation.

Sequence engine 300 includes ladder interpreter 301 for interpreting andexecuting the ladder program stored in user memory UM, and register 302for managing and storing a status of execution of the ladder program byladder interpreter 301.

Since ladder interpreter 301 has a function as a bus controller,microprocessor unit (MPU1) 201 of personal computer 200 can accessregister 302 of sequence engine 300 through personal computer expansionbus 500, and ladder interpreter 301 can access work memory 202 ofpersonal computer 200 through personal computer expansion bus 500.

I/O board 400 includes a buffer 401 which temporarily stores informationsent into and from an I/O port.

As already described, processing of the PLC can be basically classifiedinto "instruction execution" for interpreting and executing the ladderprogram and "peripheral processing" for input refreshing (IN-refreshing)and output refreshing (OUT-refreshing) of the I/O port.

In software PLC 101 with the sequence engine shown in FIG. 8 of thisembodiment, the "instruction execution" is performed by fetching anddecoding the ladder program stored in user memory UM of work memory 204in personal computer 200, and results of this "instruction execution"are reflected on I/O memory IOM of work memory 204 of personal computer200.

According to this structure, since "instruction execution" is performedby the dedicated hardware, i.e., ladder interpreter 301 of sequenceengine 300, fast processing is allowed compared with the software PLCshown in FIG. 16.

FIG. 9 is a flow chart showing steps of processing in software PLC 101with the sequence engine shown in FIG. 8. In the flow chart shown inFIG. 9, power-on and initial setting of microprocessor unit (MPU1) 201of personal computer 200 and ladder interpreter 301 of sequence engine300 are first performed (step S312) upon start-up (step S311).

Microprocessor unit (MPU1) 201 of personal computer 200 instructsstart-up of ladder interpreter 301 of sequence engine 300 (step S313).

Rudder interpreter 301 of sequence engine 300 starts up in response to astart-up instruction sent from microprocessor unit (MPU1) 201 ofpersonal computer 200 (step S411), and first operates to fetch anddecode the ladder program stored in user memory UM of work memory 204 inpersonal computer 200 (step S412). Thereby, "instruction execution" isperformed based on the ladder program (step S413).

Thereafter, the program counter provided at register 302 of sequenceengine 300 is incremented (step S415), and then it is determined whetheran end instruction issued from microprocessor unit (MPU1) 201 ofpersonal computer 200 is present or not (step S416). When it isdetermined that the end instruction is not present (NO at step S416),the process returns to step S412, and the processing from step S412 tostep S416 is repeated.

When it is determined, at step S416, that microprocessor unit (MPU1) 201of personal computer 200 has issued the end instruction (YES at stepS416), the program counter provided at register 302 of sequence engine300 is initialized (step S417), and processing by ladder interpreter 301of sequence engine 300 stops (step S418).

When ladder interpreter 301 of sequence engine 300 stops its processing,microprocessor unit (MPU1) 201 of personal computer 200 executesperipheral processing such as I/O refreshing (step S314).

Then, it is determined whether the ladder program stored in user memoryUM of work memory 204 in personal computer 200 has been completelyexecuted (step S315). When it is determined that the ladder program hasnot been completely executed (NO at step S315), the process returns tostep S313. When it is determined that the ladder program has beencompletely executed (YES at step S315), this process is finished (stepS316).

Thus, in this software PLC 101 with the sequence engine, ladderinterpreter 301 of sequence engine 300 performs "instruction execution"and more specifically, executes the user program by fetching anddecoding the ladder program stored in user memory UM of work memory 204in personal computer 200, and microprocessor unit (MPU1) 201 of personalcomputer 200 executes "peripheral processing" such as input refreshing(IN-refreshing) and output refreshing (OUT-refreshing) of the I/O port.

Thus, in this software PLC with the sequence engine, "instructionexecution" is performed by the dedicated hardware, i.e., ladderinterpreter 301 of sequence engine 300, as is done in the firstembodiment. Therefore, fast processing is allowed.

For the above steps of processing, the process includes processing of"start-up of sequence engine 300" and. "stop of sequence engine 300"based on the instructions from microprocessor unit (MPU1) 201 ofpersonal computer 200, and, for "instruction execution" by ladderinterpreter 301, register 302 of sequence engine 300 is provided withthe program counter register, status register and UM address register.

Operations such as "start-up of sequence engine 300" is similar to thosein the first embodiment, and therefore will not be described below.

Description will be given on details of the following registers, whichform register 302 of sequence engine 300 and are already described inconnection with the first embodiment.

(1) program counter register

(2) status register

(3) UM address register

FIG. 10 shows an example of the program counter register formingregister 302 of sequence engine 300.

The program counter register forming register 302 of sequence engine 300is formed of two registers, i.e., a first register 331 of 16 bits and asecond register 332 of 16 bits. In this program counter register, itsinitial value is set upon start-up of ladder interpreter 301 of sequenceengine 300, and its count value is incremented upon every execution ofone instruction of the ladder program stored in user memory UM of workmemory 202 in personal computer 200.

In eight bits from a bit 0 to a bit 7 in first register 331, there isstored an offset (H) from a UM leading address, i.e., higher eight bitsof the offset value (offset from the UM leading address) from theleading address of the ladder program stored in user memory UM for"instruction execution". In 16 bits from a bit 0 to a bit 15 in secondregister 332, there is stored an offset (L) from the UM leading address,i.e., lower 16 bits of the offset from the UM leading address. Eightbits from a bit 8 to a bit 15 in first register 331 are set to reserve.

The reserve of this program counter register is set to "0", and theinitial value is set to "00000000h".

FIG. 11 shows an example of the status register forming register 302 ofsequence engine 300.

The status register forming register 302 of sequence engine 300 isformed of one 16-bit register 333. One bit, i.e., bit 15 of register 333functions as a start flag register storing the start flag. Fifteen bitsfrom a bit 0 to a bit 14 in register 333 are set to reserve. Reserve ofthis status register is set to "0", and its initial value is set to"0000h".

When the start flag at bit 15 in the status register is "0", ladderinterpreter 301 of sequence engine 300 stops. When the start flag at bit15 in the status register is "1", ladder interpreter 301 of sequenceengine 300 starts up.

FIG. 12 shows an example of the UM address register forming register 302of sequence engine 300.

The UM address register forming register 302 of sequence engine 300 isformed of two registers, i.e., a first register 334 of 16 bits and asecond register 335 of 16 bits, and stores the leading address (UMleading address) of the ladder program stored in user memory UM for"instruction execution".

Here, 16 bits from a bit 0 to a bit 15 in first register 334 store a UMleading address H, i.e., higher 16 bits of the UM leading address, and16 bits from a bit 0 to a bit 15 in second register 335 store a UMleading address L, i.e., lower 16 bits of the UM leading address.

The initial value of this UM address register is set to "00000000h", andthis initial value is set by microprocessor unit (MPU1) 201 of personalcomputer 200 in the initial setting operation of this system.

In the above embodiment, "instruction execution" is performed by ladderinterpreter 301 of sequence engine 300. However, "instruction execution"performed by ladder interpreter 301 of sequence engine 300 may besupported by microprocessor unit (MPU1) 201 of personal computer 200.

FIG. 13 shows a modification of the second embodiment of the invention,in which "instruction execution" performed by ladder interpreter 301 ofsequence engine 300 is supported by microprocessor unit (MPU1) 201 ofpersonal computer 200. The hardware structure in this modification maybe the same as that shown in FIG. 8.

In the structure shown in FIG. 13, when microprocessor unit (MPU1) 201of personal computer 200 operates instead of ladder interpreter 301 ofsequence engine 300 to perform "instruction execution" to be performedby ladder interpreter 301 of sequence engine 300, microprocessor unit(MPU1) 201 of personal computer 200 sends an "MPU execution instruction"to ladder interpreter 301 of sequence engine 300. In this case, ladderinterpreter 301 of sequence engine 300 requests microprocessor unit(MPU1) 201 of personal computer 200 to perform "instruction execution"related to this "MPU execution instruction".

In the flow chart shown in FIG. 13, power-on and initial setting ofmicroprocessor unit (MPU1) 201 of personal computer 200 and ladderinterpreter 301 of sequence engine 300 are first performed (step S322)upon start-up of microprocessor unit (MPU1) 201 of personal computer 200(step S321).

Microprocessor unit (MPU1) 201 of personal computer 200 instructsstart-up of ladder interpreter 301 of sequence engine 300 (step S323).

Ladder interpreter 301 of sequence engine 300 starts up in response tostart instruction issued from microprocessor unit (MPU1) 201 of personalcomputer 200 (step S421), and first fetches and decodes the ladderprogram stored in user memory UM of work memory 204 in personal computer200 (step 422).

In connection with "instruction execution" of the ladder program thusfetched and decoded, it is determined whether or not microprocessor unit(MPU1) 201 of personal computer 200 has sent an "MPU executioninstruction" to ladder interpreter 301 of sequence engine 300 (stepS423). When the "MPU execution instruction" is sent (YES at step S423),an "MPU execution flag" is set (step S424), and this "instructionexecution" is requested to microprocessor unit (MPU1) 201 of personalcomputer 200.

When this "instruction execution" is requested, microprocessor unit(MPU1) 201 of personal computer 200 reads the program counter registerforming register 302 of sequence engine 300 (step S324), and thenexecutes the "MPU execution instruction" (step S326) by fetching anddecoding the ladder program stored in user memory UM of work memory 204in personal computer 200 (step S325). Thereafter, the program counterprovided at register 302 of sequence engine 300 is incremented (stepS327), and the process returns to step S422.

When it is determined that the "MPU execution instruction" is not issuedat step S423 (NO at step S423), "instruction execution" is performed atstep S425 based on the ladder program fetched and decoded at step S422.

By writing results of the execution into I/O memory IOM, the results ofexecution are reflected on I/O memory IOM (step S426).

Thereafter, the program counter provided at register 302 of sequenceengine 300 is incremented (step S427), and then it is determined whethermicroprocessor unit (MPU1) 201 of personal computer 200 has issued anend instruction or not (step S428). When it is determined that the endinstruction is not issued (NO at step S428), the process returns to stepS422, and the processing starting from step S422 is repeated.

When it is determined, at step S428, that microprocessor unit (MPU1) 201of personal computer 200 has issued the end instruction (YES at stepS428), the program counter provided at register 302 in sequence engine300 is initialized (step S429), and ladder interpreter 301 of sequenceengine 300 stops the processing (step S430).

When ladder interpreter 301 of sequence engine 300 stops the processing,microprocessor unit (MPU1) 201 of personal computer 200 executesperipheral processing such as I/O refreshing (step S328).

Then, it is determined whether the ladder program stored in user memoryUM of work memory 202 in personal computer 200 is fully completed or not(step S329). When it is determined that the ladder program is not fullycompleted (NO at step S329), the process returns to step S323. When itis determined that the ladder program is fully completed (YES at stepS329), this processing is finished.

In the modification of the second embodiment of the invention, ladderinterpreter 301 of sequence engine 300 performs "instruction execution",i.e., execution of the user program by fetching and decoding the ladderprogram stored in user memory UM of work memory 204 in personal computer200. When it receives "MPU execution instruction" from microprocessorunit (MPU1) 201 of personal computer 200, ladder interpreter 301 ofsequence engine 300 requests microprocessor unit (MPU1) 201 of personalcomputer 200 to perform "instruction execution" related to this "MPUexecution instruction", and thereby microprocessor unit (MPU1) 201 ofpersonal computer 200 can support "instruction execution" performed byladder interpreter 301 of sequence engine 300.

FIG. 14 shows an example of the status register forming register 302 ofsequence engine 300 in the structure described above.

In this case, the status register forming register 302 of sequenceengine 300 functions as a start flag register storing the start flag andan MPU execution flag register storing the MPU execution flag.

In this case, the status register forming register 302 of sequenceengine 300 is formed of one 16-bit register 336 as shown in FIG. 14. Onebit, i.e., a bit 15 in register 336 functions as a start flag registerstoring the start flag, and one bit, i.e., a bit 14 functions as an MPUexecution flag register storing the MPU execution flag. Fourteen bitsfrom a bit 0 to a bit 13 in register 336 are set to reserve. The reserveof the status register is set to "0", and the initial value is set to"0000h".

The forms of processing by ladder interpreter 301 of sequence engine 300and microprocessor unit (MPU1) 201 of personal computer 200 arecontrolled based on the start flag stored in the bit 15 of the statusregister and the MPU execution flag stored in the bit 14.

FIG. 15 is a status transition diagram showing transition of processingbased on the start flag and MPU execution flag in this modification.

In FIG. 15, a set of two numerals is added to each transition. Thenumeral at a high place represents the start flag, and the numeral at alow place represents the MPU execution flag.

In FIG. 15, when the start flag is "1" and the MPU flag is "0","instruction execution" by ladder interpreter 301 of sequence engine 300performs "instruction execution". When the start flag goes to "0" inthis state, and in other words, when the start flag goes to "0" and theMPU execution flag goes to "0", the process transfers to "peripheralprocessing" by microprocessor unit (MPU1) 201 of personal computer 200.

The start flag may go to "1" while microprocessor unit (MPU1) 201 ofpersonal computer 200 is performing "peripheral processing", and inother words, while the start flag is "0" and the MPU execution flag is"0". In other words, the start flag and MPU execution flag may go to "1"and "0", respectively. In this case, the process transfers to"instruction execution" by ladder interpreter 301 of sequence engine300.

The MPU execution flag may go to "1" while microprocessor unit (MPU1)201 of personal computer 200 is performing "peripheral processing", andin other words, when both the start flag and MPU execution flag are "0".In other words, the start flag and MPU execution flag may go to "0" and"1", respectively. Also, both the start flag and MPU execution flag maygo to "1". Thus, the start flag may go to "1", and the MPU executionflag may go to "1". In these cases, the status is determined as anerror, and the process transfers to processing for an error.

The MPU execution flag may go to "1" while ladder interpreter 301 ofsequence engine 300 is performing "instruction execution", and in otherwords, when the start flag and MPU execution flag are "1" and "0",respectively. In this case, the process transfers to "MPU executioninstruction" by microprocessor unit (MPU1) 201 of personal computer 200.

The MPU execution flag may go to "0" while microprocessor unit (MPU1)201 of personal computer 200 is performing "MPU execution instruction",and in other words, when both the start flag and MPU execution flag are"1". In this case, i.e., when the start flag and MPU execution flag goto "1" and "0", respectively, the process transfers to "instructionexecution" by ladder interpreter 301 of sequence engine 300.

The MPU execution flag may go to "1" while microprocessor unit (MPU1)201 of personal computer 200 is performing "MPU execution instruction",and in other words, when both the start flag and MPU execution flag are"1". In this case, i.e., when both the start flag and MPU execution flaggo to "1", and in such cases that the start flag goes to "0" and the MPUexecution flag goes to "1", and that both the start flag and MPUexecution flag go to "0", i.e., that the start flag goes to "0" and theMPU execution flag go to "0", the status is determined as an error, andthe process transfers to processing for an error.

The start flag and MPU execution flag may go to "0" and "1",respectively, while ladder interpreter 301 of sequence engine 300 isperforming "instruction execution", i.e., when the start flag is "1" andthe MPU execution flag is "0". In this case, the status is likewisedetermined as an error, and the process transfers to processing for anerror.

INDUSTRIAL APPLICABILITY

According to the information processing device of the invention, asdescribed above, a sequence instruction executing unit is connected to adata processing device through a bus, the sequence instruction executingunit executes a sequence instruction based on a predetermined sequenceprogram in response to an instruction issued from the data processingdevice, and the data processing device performs information processingbased on a predetermined information processing program and executesperipheral processing in accordance with a peripheral processing requestissued from a sequence instruction execution unit. Therefore, the wholesystem can be inexpensive, and an influence exerted on a cycle of thesequence processing can be minimized, which is suitable to informationprocessing.

We claim:
 1. A sequence control device comprising a data processingdevice provided with a processor and an internal bus connected to saidprocessor, and sequence instruction execution means connected to saidinternal bus, whereinsaid data processing device or said sequenceinstruction execution means includes a user memory for storing asequence program prepared by a user and an I/O memory for storing astatus of input/output, and an I/O board connected to an external devicecontrolled by an instruction of said sequence program that is connectedindependently of said sequence instruction execution means to saidinternal bus.
 2. A sequence control device comprising a data processingdevice provided with a processor and an internal bus connected to saidprocessor, and sequence instruction execution means connected to saidinternal bus, whereinsaid data processing device or said sequenceinstruction execution means includes a user memory for storing asequence program prepared by a user and an I/O memory for storing astate of input/output, an I/O board having memory means and connected toan external device is connected independently of said sequenceinstruction execution means to said internal bus, and said dataprocessing device includes processing execution means for executingpredetermined peripheral processing after interpretation and executionof an instruction in said user memory by said sequence instructionexecution means.
 3. The sequence control device according to claim 2,whereinsaid processing execution means includes:information processingexecution means for executing information processing based on apredetermined information processing program, processing interruptioncontrol means for controlling interruption of the information processingexecuted by said information processing execution means, determiningmeans for determining presence or absence of a peripheral processingrequest issued from said sequence instruction execution means uponinterruption of the information processing by said processinginterruption control means, peripheral processing execution means forexecuting said peripheral processing when said determining meansdetermines the presence of the peripheral processing request issued fromsaid sequence instruction execution means, and processing restartcontrol means for controlling restart of the information processinginterrupted by said processing interruption control means.
 4. Thesequence control device according to claim 3, whereinsaid informationprocessing program is formed of a plurality of blocks, and saidinformation processing execution means executes the informationprocessing a block at a time.
 5. The sequence control device accordingto claim 4, whereinsaid determining means determines the presence orabsence of the peripheral processing request issued from said sequenceinstruction execution means upon every completion of said informationprocessing performed a block at a time.
 6. The sequence control deviceaccording to claim 2, whereinsaid sequence program is formed of a ladderprogram, and said sequence instruction execution means includes a ladderinterpreter performing instruction execution processing by interpretingand executing said ladder program.
 7. The sequence control deviceaccording to claim 6, whereinsaid sequence instruction execution meansincludes register means for managing the instruction executionprocessing by said ladder interpreter.
 8. The sequence control deviceaccording to claim 7, whereinsaid register means includes:a programcounter register having a value to be initially set upon start-up ofsaid ladder interpreter and incremented upon every execution of oneinstruction of said ladder program, a status register storing a statusof execution of the ladder program by said ladder interpreter, and anaddress register storing a leading address of the ladder programexecuted by said ladder interpreter.
 9. The sequence control deviceaccording to claim 8, whereinsaid status register stores a start flagindicating start and stop of said ladder interpreter.
 10. The sequencecontrol device according to claim 9, whereinsaid ladder interpreterperforms said instruction execution processing based on the leadingaddress stored in said address register when said start flag indicatesstart-up of said ladder interpreter, and requests said data processingdevice to perform said peripheral processing when said start flagindicates stop of said ladder interpreter.
 11. The sequence controldevice according to claim 9, whereinsaid start flag is written into saidstatus register based on an instruction issued from said data processingdevice.
 12. The sequence control device according to claim 2, furthercomprising:sequence program execution support means for executing asequence program stored in said user memory instead of said sequenceinstruction execution means.
 13. The sequence control device accordingto claim 8, whereinsaid status register stores a first flag indicatingstart and stop of said ladder interpreter, and a second flag indicatingwhether said instruction execution processing by said ladder interpreteris to be requested to said data processing device or not.
 14. Thesequence control device according to claim 13, whereinsaid ladderinterpreter executes said instruction execution processing based on theleading address stored in said address register, when said first flagindicates start-up of said ladder interpreter and said second flag doesnot indicate a request to said data processing device for saidinstruction execution processing; requests said data processing deviceto perform said instruction execution processing when said first flagindicates start-up of said ladder interpreter and said second flagindicates a request to said data processing device for said instructionexecution processing; and requests said data processing device toperform peripheral processing such as refreshing of the I/O port whensaid start flag indicates stop of said ladder interpreter and saidsecond flag does not indicate a request to said data processing devicefor said instruction execution processing.
 15. The sequence controldevice according to claim 13, whereina process is determined as an errorand processing for an error is executed in such a case, during saidinstruction execution processing by said ladder interpreter, that saidfirst flag indicates stop of said ladder interpreter and said secondflag indicates a request to said data processing device for saidinstruction execution processing; in such cases, during said instructionexecution processing by said data processing device, that said firstflag indicates start-up of said ladder interpreter and said second flagindicates a request to said data processing device for said instructionexecution processing, that said first flag indicates stop of said ladderinterpreter and said second flag indicates a request to said dataprocessing device for said instruction execution processing, and thatsaid start flag indicates stop of said ladder interpreter and saidsecond flag does not indicate a request to said data processing devicefor said instruction execution processing; and in such cases, duringsaid peripheral processing by said data processing device, that saidfirst flag indicates start-up of said ladder interpreter and said secondflag indicates a request to said data processing device for saidinstruction execution processing, and that said first flag indicatesstop of said ladder interpreter and said second flag indicates a requestto said data processing device for said instruction executionprocessing.
 16. The sequence control device according to claim 13,whereinsaid first and second flags are written into said status registerbased on an instruction issued from said data processing device.
 17. Asequence control method comprising the step of:connecting a sequenceinstruction execution unit to a data processing device through a bus,whereinsaid sequence instruction execution unit executes a sequenceinstruction based on a predetermined sequence program in response to aninstruction issued from said data processing device, and said dataprocessing device performs information processing based on apredetermined information processing program, and executes peripheralprocessing in accordance with a peripheral processing request issuedfrom said sequence instruction execution unit.
 18. The sequence controlmethod according to claim 17, wherein said data processingdevice:determines presence or absence of the peripheral processingrequest issued from said sequence instruction execution unit duringinformation processing based on a predetermined information processingprogram, interrupts said information processing to execute theperipheral processing when it is determined that the peripheralprocessing request issued from said sequence instruction execution unitis present, and restarts said information processing after completion ofsaid peripheral processing.
 19. The sequence control method according toclaim 17, whereinsaid information processing program is formed of aplurality of blocks, said data processing device determines presence orabsence of the peripheral processing request issued from said sequenceinstruction execution unit upon every completion of informationprocessing performed a block at a time, said information processing isinterrupted and said peripheral processing is executed when it isdetermined that the peripheral processing request issued from saidsequence instruction execution unit is present, and said informationprocessing is restarted after completion of said peripheral processing.20. The sequence control method according to claim 19, whereininternalcontents of the interrupted information processing are saved uponinterruption of said information processing, and restart of saidinformation processing is performed based on the saved internal contentsof said information processing.
 21. The sequence control methodaccording to claim 17, whereinsaid sequence program is formed of aladder program, and said sequence instruction execution unit executessaid ladder program by interpreting said ladder program.
 22. A sequencecontrol method comprising the steps of:connecting a sequence instructionexecution unit to a data processing device through a bus, and storing asequence program in said data processing device, whereinsaid sequenceinstruction execution unit executes said sequence program by accessingthrough said bus said sequence program stored in said data processingdevice based on an instruction issued from said data processing device.23. A sequence control method comprising the steps of:connectingsequence instruction execution unit to a data processing device througha bus, and storing a sequence program in said data processing device,wherein said sequence instruction execution unit either executes saidsequence program by accessing, through said bus, said sequence programstored in said data processing device based on an instruction issuedfrom said data processing device, or said sequence instruction executionunit requests said data processing device to execute said sequenceprogram in accordance with an instruction issued from said dataprocessing device, and restarts execution by said sequence executioninstruction unit when the requested execution of said sequence programby said data processing device is completed.
 24. The sequence controlmethod according to claim 22, whereinsaid sequence instruction executionunit finishes execution of said sequence program, and requests said dataprocessing device to execute a peripheral processing in accordance withan instruction issued from said data processing device.
 25. The sequencecontrol method according to claim 22, whereinsaid sequence instructionexecution unit is provided with a register for managing execution ofsaid sequence program, a start flag indicating start and stop of saidsequence instruction execution unit is written into said register inaccordance with an instruction issued from said data processing device,and start and stop of said data processing device are controlled withreference to said written start flag.
 26. The sequence control methodaccording to claim 22, whereinsaid sequence instruction execution unitis provided with a register for managing execution of said sequenceprogram, a start flag indicating start and stop of said sequenceinstruction execution unit and a second flag indicating whether saiddata processing device is to be requested to perform the instructionexecution processing to be performed by said sequence instructionexecution unit are written into said register in accordance with aninstruction issued from said data processing device, and start and stopof said data processing device and requests to said data processingdevice for the instruction execution processing and the peripheralprocessing are controlled with reference to said written first andsecond flags.
 27. A sequence engine comprising:a ladder interpreterconnected to an internal bus of a data processing device, and started upby said data processing device for executing a ladder instruction byinterpreting said ladder instruction; and a register for managing andstoring a status of execution of a ladder program by said ladderinterpreter, whereinsaid sequence engine does not have a function ofexecuting peripheral processing.
 28. A storage medium applied to ansequence control device, whereinsaid sequence control device includes:adata processing device having a processor and an internal bus connectedto said processor, a sequence instruction execution unit connected tosaid internal bus, a user memory for storing a sequence program and anI/O memory for storing a status of input/output, said user memory andsaid I/O memory being provided at said data processing device or saidsequence instruction execution unit, and an I/O board connected to anexternal device controlled by an instruction of said sequence program,and connected independently of said sequence instruction execution unitto said internal bus; and wherein said storage medium stores a programfor executing peripheral processing by said data processing device, saidperipheral processing including I/O refreshing performed by storing datasupplied from said external device and stored in a storage unit of saidI/O board in said I/O memory after interpretation and execution of theinstruction in said user memory by said sequence instruction executionunit, and by outputting the data in said I/O memory to said externaldevice through said I/O board.